The present invention relates to a memory device incorporated in a semiconductor device.
The recent trend of increased capacity, better performing and functionally superior semiconductor memory devices is striking, and the range of applicable use of such devices seems infinite. Against this background, requirements for advanced and high speed memories are rapidly becoming more prevalent as represented, for example, by the popularity of superhigh-speed large-sized computers and high performance work stations, the development of 32-bit personal computers, and applications in the video arts. To satisfy such requests for higher speed large-capacity memories, it is essential to increase the circuit technology speed, as well as to increase the device technology.
As for the circuit technology, particularly in the dynamic random access memory (DRAM), high speed access mode functions such as page mode, nibble mode and serial mode are proposed and realized. Such access mode functions which increase the speed using circuit technology which is presumed to be more important henceforth.
As a conventional semiconductor memory device, hereinafter, an example of a DRAM having an increased in memory speed using the nibble mode function is illustrated below.
FIG. 8 is a block diagram of a conventional DRAM data reading and writing circuit having an increased memory speed using the nibble mode function, FIG. 9 is a detailed circuit diagram of essential portions of the circuit shown in FIG. 8, FIG. 10 is a block diagram of an internal signal generating circuit for driving the circuits shown in FIG. 8 and FIG. 9, and FIG. 11 depicts voltage waveform diagrams at each node in the circuits shown in FIG. 8, FIG. 9, and FIG. 10.
Referring to FIG. 8, a row address buffer 1 and a column address buffer 2 generate an internal row address signal and an internal column address signal, depending on the address signal input provided at the individual address input terminals. A row decoder 3 and a word line driver 4, responding to the internal row address signal, select one of the plural word lines, and choose the memory cells one line from a memory cell array 5 arranged in a matrix form of rows and columns. A sense amplifier 6, when reading out the data, amplifies the data being read out from the memory cell connected to the selected word line, and latches on the bit line which corresponds a row line. Furthermore, a column decoder 7, in response to the internal column address signal, selects a necessary number (four, in this example) of bit lines out of the plural bit lines, and transfers the data on the selected bit lines to data lines.
Data lines are provided in four pairs. Each data line is composed of two mutually complementary signal lines (when one is at high level, the other is at low level), that is, DL1, DL1; DL2, DL2; DL3, DL3; DL4, DL4. When reading out data, data latch 8 shown in FIG. 8 is responsible for amplifying the data transferred from the bit line selected by the column decoder 7 to the data line, and latching the data on the data line. This data latch 8 is composed of four latch circuits 9 to 12 corresponding to each pair of the data lines, and these latch circuits 9 to 12 are composed of differential amplifiers, such as dynamic flip-flops. A selector 14 selects an arbitrary one of the four pairs of data lines, and exchanges data between a data input buffer 13 or data output buffer 15, and the selected data line. A counter 16 provides address information for determining the selection of the data line in the selector 14, and it is mainly composed of a two-bit binary counter for counting by starting from the two-bit address signal corresponding to each bit of the row address and column address of the internal address signal generated by the row address buffer 1 and column address buffer 2.
FIG. 9 shows a detailed circuit composition of the data latch 8 and selector 14 which are particularly closedly related with the realization of the nibble mode function in the shown in FIG. 8.
The selector 14 is composed of MIS transistors Q1 to Q16 and logic gates G1 to G4. Depending on the output signals C1 to C4 and internal write control signal W of the counter 16 shown in FIG. 8, control signals W1 to W4 are generated from the logic gates G1 to G4. On the basis of these control signals W1 to W4, in the write mode, the data D1, D1 generated in the data input buffer 13 shown in FIG. 8 are transferred to the selected data lines through the transistors Q1 to Q8, and in the read mode, the data D0, D0 are supplied into the data output buffer 15 shown in FIG. 8, through the transistors Q9 to Q16.
The circuits shown in FIG. 8 and FIG. 9 are driven by the clock signals generated by the internal clock generating circuit shown in FIG. 10. The internal clock generating circuit shown in FIG. 10 is composed of clock generators 17 to 19, address transition detector 20, and logic gate G5.
RAS, CAS, WE and the address signal input are signals provided from external the memory device. RAS is a reference clock signal for driving the row address buffer 1, row decoder 3, word line driver 4, sense amplifier 6 and data latch 8 shown in FIG. 8. CAS is a reference clock signal for driving the column address buffer 2, column decoder 7, selector 14, counter 16, data input buffer 13 and data output buffer 15 in the active period of RAS (while RAS is at low level as mentioned later). WE is a signal for specifying whether the memory device is in read mode or in the write mode, and practically, in read mode, by the clock generator 18, the internal reading control signal (clock signal) R is set in an active state (high level), and in the write mode, the internal writing control signal (clock signal) W is set in an active state (high level).
In thus composed semiconductor memory device (DRAM in this conventional example), the nibble mode operation is described below while referring to the timing charts shown in FIG. 11, and the circuit diagrams shown in FIGS. 8, 9, 10.
The nibble mode function is as shown in the timing chart of FIG. 11. That is, by feeding the second reference clock signal CAS plural times (in other words, by setting CAS at low level plural times as shown, or four times in FIG. 11, t4 to t5, t6 to t7, t8 to t9, t10 to t11) in the active period of the first reference clock signal RAS (that is, while the RAS is at low level), the data is read out or written in at a high speed at every input of CAS. At this time, the designation of the memory cell subjected to reading or writing at every input of CAS, that is, the designation of row and column addresses, is sufficient only with the designation of the row address by the address input signal in the active state of RAS [in other words, in the fall of RAS (time t1)], and the designation of the column address at the time of the first input of CAS (time t4). At the time of the subsequent CAS input, without designation of the address by the address signal input, only by the designation of the output signals C1 to C4 of the counter 16 in the memory device, reading and writing is executed sequentially in the four memory cells corresponding to four bits starting with the address specified at the time of the first CAS input. In particular, as for the reading of data of every input of CAS, the data already latched in the data latch 8 is selected by the counter 16 and selector 14, and it is sufficient to transfer to the data output buffer 15. Therefore, unlike the ordinary reading, since it is not necessary to operate the column decoder or data latch by newly specifying the column address, the memory speed may be notably higher. In the example of FIG. 11, CAS input is made four times in the RAS active period, and the first time and third time are data writing, and second time and fourth time are data reading. First, at time t1, RAS becomes a low level, and the row address buffer 1, row decoder 3, sense amplifier 6 and others are put into action, and the data from the memory cells are latched on the bit lines. Next, at time t2, receiving selection of bit lines by the column decoder 7 and data transferred to data lines, the data latch driving signal PE is activated at time t3, and the data latch 8 is actuated. As a result, data is latched in the data lines DL1, DL1 to DL4, DL4. Next, a first CAS is fed (time t4). At this time, the write control signal WE is at low level, that is, the CAS cycle is specified in a data write cycle, and therefore, correspondingly, the internal write control signal W is activated, thereby becoming a high level. By contrast, at the time of the second CAS input (time t6), since the write control signal WE is at high level, this cycle becomes a data read cycle, and the internal read control signal R is activated. On the other hand, as for the output signals C1 to C4 of the counter 16 for controlling the quarter selector 14, first, according to the designation of the column address determined at time t2, at the time of the first CAS input (time t4), the output signal C1 is already in an active state (high level), and on every occasion of the subsequent CAS inputs (time t5, t7, t9), the output signals C2, C3, C4 are sequentially activated. Thus, at the time of the first CAS input (time t4), the internal write control signal W and output signal C1 are in an active state. In consequence, by the action of the logic gate in FIG. 9, the control signal W1 becomes a high level, and the transistors Q1, Q2 are made to conduct, and the write data is written in data lines DL1, DL1, and is further written into the memory cells through bit lines. By contrast, at the time of the second CAS input (time t6), the internal write control signal W is in an inactive state, while the internal read control signal R and output signal C2 are in an active state. As a result, by the internal read control signal R, the data output buffer 15 in FIG. 8 becomes ready to act, and the data D0, D0 transferred to the data output buffer 15 through transistors Q11, Q12 in FIG. 9 (the data being latched in DL2, DL2 at time t3) are read out at the data output terminal as the read data output. The operation at the time of the third and fourth CAS inputs is basically same as in the first and second inputs, except that the states of C1 to C4 are different, and a detailed explanation thereof is omitted.
Thus, in the conventional semiconductor memory device, at the time of the second and subsequent inputs of the reference clock corresponding to CAS, the address signal input is omitted, and the data latched on plural pairs of data lines can be delivered by synchronizing with the reference clock sequentially by the counter 16 and the selector 14 driven by the output signals C1 to C4 of the counter 16, the data reading speed is markedly increased.
However, with regard to the writing of data, there is no substantial difference from the operation in the ordinary mode, and a high speed writing operation is not expected using the access mode functions, such as the nibble mode. In other words, in the conventional circuit composition, writing of data requires transfer of data from the data input buffer 13 to the selector 14, data lines, sense amplifier 6, bit lines, and the memory cell directly. Therefore, all loads, such as floating loads parasitizing these circuit blocks, must be handled by the data input buffer 13 alone so as to drive all these circuit blocks. Since the loads tend to increase as the memory capacity becomes larger, they are substantial barriers against increasing the speed of the memory write action. Hence, in order to keep a sufficient writing time, it is required to maintain the input cycle time of the reference clock in a high speed mode over a specific period, and the action time of the memory is regulated by the data write time. Thus, in the semiconductor memory device of the conventional structure, an increase in the memory speed is limited by the data write speed.
It is hence a primary object of the present invention to solve the problems of the prior art and to present a high speed memory device having a sufficient timing margin.